The present invention relates to failure analysis of integrated circuits and more particularly to a method and system of performing failure analysis on multilayer silicon-on-insulator (SOI) devices.
Failure analysis is becoming an increasingly important aspect of the fabrication process for integrated circuits. As device geometries become smaller, the probability of defects occurring increases, as well as the deleterious impact the defects have on the device.
One common failure analysis technique is to examine the structures of the integrated circuit device under a scanning electron microscope (SEM) in an attempt to identify structural defects. In most integrated circuits, multiple layers of metal traces are formed over active devices, such as transistors. Using an SEM that normally has an acceleration voltage ranging between 0 and 30 kilovolts, an operator may view device structures that are located three layers deep from the top of the device.
Current submicron microprocessors, however, may have up to nine layers (M1-M6) of copper metallization, and future designs may have many more, perhaps as high as nine to ten layers. Therefore, it is becoming more difficult to examine transistors from the top the device due to the many intervening layers of metal. High-voltage (HV) SEM""s that have acceleration voltages up to 200 kilovolts have been commercially available as analytical instruments. Even with the use of HV SEM""s, however, defects located six or more layers deep are not visible. In other words, front-side viewing of an integrated circuit device containing 6-9 copper metal layers will fail to reveal defects on layers M3-M1 and on the active device layer.
One approach to overcome this problem is to selectively delayer the device using chemical polishing or wet/dry etching in order to remove the upper layers of metal. Although this approach is effective for some types of devices, delayering is not as effective with copper metallization due to the difficulty in removing copper one layer at a time. Furthermore, delayering ruins the functionality the device and once this type of the failure analysis is performed, the device cannot be powered up for further testing.
Accordingly, what is needed is improved method for performing failure analysis on integrated circuits having multiple layer of copper interconnects.
The present invention provides a method for performing backside analysis on a silicon-on-insulator device composing a silicon substrate layer, a buried oxide layer (BOX), an active layer containing active devices, and multiple metal layers. The method includes opening a window in the silicon layer using the BOX layer as a stop, and using the window as a field of view to view structures in the active layer with a microscope, wherein defects can be detected in the device without delayering any of the metal layers, such that the device remains functional for testing.
According to the method and system disclosed herein, in the embodiment where HV SEM is used to view the backside of the device, defects may be detected in the device up through layers M3 or M4. In addition, the device structures may be examined without delayering any of the metal layers of the device, such that the device is still essentially functional and could be powered-up during testing to observe device signals as well.